1. Field of Invention
The present invention relates to the field of electronic design automation systems. In particular, the invention describes a memory model that can be used in electronic design automation systems.
2. Description of Related Art
Electronic design automation is a field of engineering where designers use computer systems and tools executing on those computer systems to design electronic circuits.
One of the goals of electronic design automation is to automate many of the design steps to allow designers to design circuits faster and cheaper than before. Example tools used by designers are a synthesis tool and a simulator. The synthesis tool allows a designer to provide the synthesis tool with a high level language description of a circuit, and the synthesis tool generates the corresponding circuit. A simulator allows a designer to simulate the operation of a circuit with different stimuli using a description of the circuit.
The description of the electronic circuit, often written in VHDL or Verilog, defines the operation of the circuit at a high level. That is, the description is a model of the circuit. A circuit model can be written to represent many different kinds of electronic circuits, for example, a multiplier, an arithmetic logic unit, a microprocessor, a PCI bus interface, etc.
Circuit models can be very complex. This adds to the amount of computing resources (memory and processing time) a given synthesis tool or simulator will need to process the circuit model. For simulation, it is desirable to simulate very larger circuits. For example, it is desirable to stimulate an entire computer system during the booting of the UNIX operating system. This requires a circuit model of the computer system. However, such a model would require large amounts of computing resources. For example, the computer model would need to include a model of a large amount of different kinds of memory (e.g. hard disk, RAM, ROM).
In previous systems, a circuit model of a memory (a memory model) in a simulator is represented by an array. During a simulation, each instance of a particular memory model causes the simulator to allocate a portion of the simulator memory to represent that memory model. For example, if a memory model represents a 4 Kbytes RAM, then the simulator instantiates a 4 Kbytes array to hold the data written to the 4 Kbytes RAM memory model. Thus, the previous simulator can simulate a RAM in a circuit.
However, this simulation technique has a number of drawbacks when applied to large memory models. Assume that a memory model of a large amount of RAM is to be used in a simulator, e.g. a memory system including 256 one Mbytes SIMMs. Further assume that the computer system upon which the simulator is executing only has 128 Mbytes of RAM. A previous simulator would attempt to allocate 256 one Mbytes arrays to represent the 256 one Mbytes SIMMs. Depending on the type of computer system upon which the previous simulator was executing, this would result in an error that would stop the simulation, or this would cause a large amount of very slow virtual memory to be used, significantly slowing the simulation (e.g. the extra 128 Mbytes of RAM would be allocated from a hard drive). It is highly unlikely that all this memory will be accessed during the simulation, but the prior art systems allocated the memory regardless. Therefore, it has been determined that a more efficient memory model should be supported in a simulator tool.
Another problem with using the previous memory models in simulation, and synthesis, is that there is little standardization among the memory models. One vendor will supply one type of interface to his/her memory models, while another vendor will supply another type of interface to his/her memory models. A designer must learn each type of interface, while the simulation tool must support each underlying memory model. Similarly, a synthesis tool must use special cases to synthesize a corresponding memory for each of the corresponding memory models. Therefore, it has been determined that a standardized memory model should be supported for a synthesis tool and a simulator.